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1 1-megabit 2.7-volt only serial dataflash ? at45db011 preliminary features ? single 2.7v - 3.6v supply ? serial interface architecture ? page program operation C single cycle reprogram (erase and program) C 512 pages (264 bytes/page) main memory ? optional page and block erase operations ? one 264-byte sram data buffer ? internal program and control timer ? fast page program time C 7 ms typical ? 120 m s typical page to buffer transfer time ? low-power dissipation C 4 ma active read current typical C2 m a cmos standby current typical ? 13 mhz max clock frequency ? hardware data protection feature ? serial peripheral interface (spi) compatible C modes 0 and 3 ? cmos and ttl compatible inputs and outputs ? commercial and industrial temperature ranges description the at45db011 is a 2.7-volt only, serial interface flash memory suitable for in-sys- tem reprogramming. its 1,081,344 bits of memory are organized as 512 pages of 264 bytes each. in addition to the main memory, the at45db011 also contains one sram data buffer of 264 bytes. unlike conventional flash memories that are accessed ran- domly with multiple address lines and a parallel interface, the dataflash uses a serial interface to sequentially access its data. the simple serial interface facilitates hard- rev. 1103cC08/98 pin configurations pin name function cs chip select sck serial clock si serial input so serial output wp hardware page write protect pin reset chip reset rdy/busy ready/busy (continued) tssop top view type 1 1 2 3 4 5 6 7 14 13 12 11 10 9 8 rdy/busy reset wp vcc gnd sck so cs nc nc nc nc nc si plcc 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 sck si so nc nc nc nc nc nc wp reset rdy/busy nc nc nc nc nc nc 4 3 2 1 32 31 30 14 15 16 17 18 19 20 nc nc dc dc nc nc nc cs nc nc gnd vcc nc nc soic 1 2 3 4 8 7 6 5 si sck reset cs so gnd vcc wp note: plcc package pins 16 and 17 are dont connect at45db011 preliminary 16- megabit 2.7-volt only serial dataflash
at45db011 2 ware layout, increases system reliability, minimizes switch- ing noise, and reduces package size and active pin count. the device is optimized for use in many commercial and industrial applications where high density, low pin count, low voltage, and low power are essential. typical applica- tions for the dataflash are digital voice storage, image storage, and data storage. the device operates at clock frequencies up to 13 mhz with a typical active read current consumption of 4 ma. to allow for simple in-system reprogrammability, the at45db011 does not require high input voltages for pro- gramming. the device operates from a single power sup- ply, 2.7v to 3.6v, for both the program and read operations. the at45db011 is enabled through the chip select pin (cs ) and accessed via a three-wire interface consisting of the serial input (si), serial output (so), and the serial clock (sck). all programming cycles are self-timed, and no separate erase cycle is required before programming. block diagram memory array to provide optimal flexibility, the memory array of the at45db011 is divided into three levels of granularity com- prising of sectors, blocks, and pages. the memory archi- tecture diagram illustrates the breakdown of each level and details the number of pages per sector and block. all pro- gram operations to the dataflash occur on a page by page basis; however, the optional erase operations can be per- formed at the block or page level. flash memory array page (264 bytes) buffer (264 bytes) i/o interface sck cs reset v cc gnd rdy/busy wp so si
at45db011 3 memory architecture diagram device operation the device operation is controlled by instructions from the host processor. the list of instructions and their associated opcodes are contained in tables 1 and 2. a valid instruc- tion starts with the falling edge of cs followed by the appro- priate 8-bit opcode and the desired buffer or main memory address location. while the cs pin is low, toggling the sck pin controls the loading of the opcode and the desired buffer or main memory address location through the si (serial input) pin. all instructions, addresses, and data are transferred with the most significant bit (msb) first. read by specifying the appropriate opcode, data can be read from the main memory or from the data buffer. main memory page read: a main memory read allows the user to read data directly from any one of the 512 pages in the main memory, bypassing the data buffer and leaving the contents of the buffer unchanged. to start a page read, the 8-bit opcode, 52h, is followed by 24 address bits and 32 dont care bits. in the at45db011, the first six address bits are reserved for larger density devices (see notes on page 9), the next nine address bits (pa8- pa0) specify the page address, and the next nine address bits (ba8-ba0) specify the starting byte address within the page. the 32 dont care bits which follow the 24 address bits are sent to initialize the read operation. following the 32 dont care bits, additional pulses on sck result in serial data being output on the so (serial output) pin. the cs pin must remain low during the loading of the opcode, the address bits, and the reading of data. when the end of a page in main memory is reached during a main memory page read, the device will continue reading at the beginning of the same page. a low to high transition on the cs pin will terminate the read operation and tri-state the so pin. buffer read: data can be read from the data buffer using an opcode of 54h. to perform a buffer read, the eight bits of the opcode must be followed by 15 dont care bits, nine address bits, and eight don't care bits. since the buffer size is 264-bytes, nine address bits (bfa8-bfa0) are required to specify the first byte of data to be read from the buffer. the cs pin must remain low during the loading of the opcode, the address bits, the dont care bits, and the reading of data. when the end of the buffer is reached, the device will continue reading back at the beginning of the buffer. a low to high transition on the cs pin will terminate the read operation and tri-state the so pin. main memory page to buffer transfer: a page of data can be transferred from the main memory to buffer. an 8-bit opcode of 53h is followed by the six reserved bits, nine address bits (pa8-pa0) which specify the page in block = 2112 bytes (2k + 64) 8 pages block 0 block 1 block 2 block 62 block 63 block 61 page = 264 bytes (256 + 8) page 0 page 1 page 6 page 7 page 8 page 9 page 510 page 511 block 0 page 14 page 15 page 16 page 17 page 18 page 509 block 1 block architecture page architecture sector 0 = 2112 bytes (2k + 64) sector 1 = 65,472 bytes (62k + 1984) sector architecture sector 2 = 67,584 bytes (64k + 2k) block 3 block 29 block 30 block 31 block 32 block 33 block 34 sector 1 sector 2 sector 0
at45db011 4 main memory that is to be transferred, and nine dont care bits. the cs pin must be low while toggling the sck pin to load the opcode, the address bits, and the dont care bits from the si pin. the transfer of the page of data from the main memory to the buffer will begin when the cs pin tran- sitions from a low to a high state. during the transfer of a page of data (t xfr ), the status register can be read to deter- mine whether the transfer has been completed or not. main memory page to buffer compare: a page of data in main memory can be compared to the data in the buffer. an 8-bit opcode of 60h is followed by 24 address bits consisting of the six reserved bits, nine address bits (pa8-pa0) which specify the page in the main memory that is to be compared to the buffer, and nine dont care bits. the loading of the opcode and the address bits is the same as described previously. the cs pin must be low while tog- gling the sck pin to load the opcode, the address bits, and the don't care bits from the si pin. on the low to high transi- tion of the cs pin, the 264 bytes in the selected main mem- ory page will be compared with the 264 bytes in the buffer. during this time (t xfr ), the status register will indicate that the part is busy. on completion of the compare operation, bit 6 of the status register is updated with the result of the compare. program buffer write: data can be shifted in from the si pin into the data buffer. to load data into the buffer, an 8-bit opcode of 84h is followed by 15 dont care bits and nine address bits (bfa8-bfa0). the nine address bits specify the first byte in the buffer to be written. the data is entered following the address bits. if the end of the data buffer is reached, the device will wrap around back to the beginning of the buffer. data will continue to be loaded into the buffer until a low to high transition is detected on the cs pin. buffer to main memory page program with built-in erase: data written into the buffer can be pro- grammed into the main memory. an 8-bit opcode of 83h is followed by the six reserved bits, nine address bits (pa8- pa0) that specify the page in the main memory to be writ- ten, and nine additional dont care bits. when a low to high transition occurs on the cs pin, the part will first erase the selected page in main memory to all 1s and then program the data stored in the buffer into the specified page in the main memory. both the erase and the programming of the page are internally self timed and should take place in a maximum time of t ep . during this time, the status register will indicate that the part is busy. buffer to main memory page program with- out built-in erase: a previously erased page within main memory can be programmed with the contents of the buffer. an 8-bit opcode of 88h is followed by the six reserved bits, nine address bits (pa8-pa0) that specify the page in the main memory to be written, and nine additional dont care bits. when a low to high transition occurs on the cs pin, the part will program the data stored in the buffer into the specified page in the main memory. it is necessary that the page in main memory that is being programmed has been previously erased. the programming of the page is internally self timed and should take place in a maximum time of t p . during this time, the status register will indicate that the part is busy. page erase: the optional page erase command can be used to individually erase any page in the main memory array allowing the buffer to main memory page program without built-in erase command to be utilized at a later time. to perform a page erase, an opcode of 81h must be loaded into the device, followed by six reserved bits, nine address bits (pa8-pa0), and nine dont care bits. the nine address bits are used to specify which page of the memory array is to be erased. when a low to high transition occurs on the cs pin, the part will erase the selected page to 1s. the erase operation is internally self-timed and should take place in a maximum time of t pe . during this time, the status register will indicate that the part is busy. block erase: a block of eight pages can be erased at one time allowing the buffer to main memory page pro- gram without built-in erase command to be utilized to reduce programming times when writing large amounts of data to the device. to perform a block erase, an opcode of 50h must be loaded into the device, followed by six reserved bits, six address bits (pa8-pa3), and 12 dont care bits. the six address bits are used to specify which block of eight pages is to be erased. when a low to high transition occurs on the cs pin, the part will erase the selected block of eight pages to 1s. the erase operation is internally self-timed and should take place in a maximum time of t be . during this time, the status register will indicate that the part is busy.
at45db011 5 main memory page program: this operation is a combination of the buffer write and buffer to main memory page program with built-in erase operations. data is first shifted into the buffer from the si pin and then programmed into a specified page in the main memory. an 8-bit opcode of 82h is followed by the six reserved bits and 18 address bits. the nine most significant address bits (pa8-pa0) select the page in the main memory where data is to be written, and the next nine address bits (bfa8-bfa0) select the first byte in the buffer to be written. after all address bits are shifted in, the part will take data from the si pin and store it in the data buffer. if the end of the buffer is reached, the device will wrap around back to the beginning of the buffer. when there is a low to high transition on the cs pin, the part will first erase the selected page in main memory to all 1s and then program the data stored in the buffer into the specified page in the main memory. both the erase and the programming of the page are internally self timed and should take place in a maximum of time t ep . during this time, the status register will indicate that the part is busy. auto page rewrite: this mode is only needed if multi- ple bytes within a page or multiple pages of data are modi- fied in a random fashion. this mode is a combination of two operations: main memory page to buffer transfer and buffer to main memory page program with built-in erase. a page of data is first transferred from the main memory to the data buffer, and then the same data (from the buffer) is programmed back into its original page of main memory. an 8-bit opcode of 58h is followed by the six reserved bits, nine address bits (pa8-pa0) that specify the page in main memory to be rewritten, and nine additional dont care bits. when a low to high transition occurs on the cs pin, the part will first transfer data from the page in main memory to the buffer and then program the data from the buffer back into same page of main memory. the operation is internally self-timed and should take place in a maximum time of t ep . during this time, the status register will indicate that the part is busy. if a sector is programmed or reprogrammed sequentially page by page, then the programming algorithm shown in figure 1 is recommended. otherwise, if multiple bytes in a page or several pages are programmed randomly in a sec- tor, then the programming algorithm shown in figure 2 is recommended. status register: the status register can be used to determine the devices ready/busy status, the result of a main memory page to buffer compare operation, or the device density. to read the status register, an opcode of 57h must be loaded into the device. after the last bit of the opcode is shifted in, the eight bits of the status register, starting with the msb (bit 7), will be shifted out on the so pin during the next eight clock cycles. the five most-signifi- cant bits of the status register will contain device informa- tion, while the remaining three least-significant bits are reserved for future use and will have undefined values. after bit 0 of the status register has been shifted out, the sequence will repeat itself (as long as cs remains low and sck is being toggled) starting again with bit 7. the data in the status register is constantly updated, so each repeating sequence will output new data. ready/busy status is indicated using bit 7 of the status reg- ister. if bit 7 is a 1, then the device is not busy and is ready to accept the next command. if bit 7 is a 0, then the device is in a busy state. the user can continuously poll bit 7 of the status register by stopping sck once bit 7 has been output. the status of bit 7 will continue to be output on the so pin, and once the device is no longer busy, the state of so will change from 0 to 1. there are eight operations which can cause the device to be in a busy state: main memory page to buffer transfer, main memory page to buffer compare, block erase addressing pa8 pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 block 000000xxx0 000001xxx1 000010xxx2 000011xxx3 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 111100xxx60 111101xxx61 111110xxx62 111111xxx63
at45db011 6 buffer to main memory page program with built-in erase, buffer to main memory page program without built-in erase, page erase, block erase, main memory page pro- gram, and auto page rewrite. the result of the most recent main memory page to buffer compare operation is indicated using bit 6 of the status register. if bit 6 is a 0, then the data in the main memory page matches the data in the buffer. if bit 6 is a 1, then at least one bit of the data in the main memory page does not match the data in the buffer. the device density is indicated using bits 5, 4, and 3 of the status register. for the at45db011, the three bits are 0, 0, and 1. the decimal value of these three binary bits does not equate to the device density; the three bits represent a combinational code relating to differing densities of serial dataflash devices, allowing a total of eight different density configurations. hardware page write protect: if the wp pin is held low, the first 256 pages of the main memory cannot be reprogrammed. the only way to reprogram the first 256 pages is to first drive the protect pin high and then use the program commands previously mentioned. the wp pin is internally pulled high; therefore, in low pin count applica- tions, connection of the wp pin is not necessary if this pin and feature will not be utilized. however, it is recom- mended that the wp pin be driven high externally when- ever possible. reset : a low state on the reset pin (reset ) will terminate the operation in progress and reset the internal state machine to an idle state. the device will remain in the reset condition as long as a low level is present on the reset pin. normal operation can resume once the reset pin is brought back to a high level. the device incorporates an internal power-on reset circuit, so there are no restrictions on the reset pin during power-on sequences. the reset pin is also internally pulled high; therefore, in low pin count applications, con- nection of the reset pin is not necessary if this pin and feature will not be utilized. however, it is recommended that the reset pin be driven high externally whenever possible. ready/busy : this open drain output pin will be driven low when the device is busy in an internally self-timed oper- ation. this pin, which is normally in a high state (through an external pull-up resistor), will be pulled low during program- ming operations, compare operations, and during page-to- buffer transfers. the busy status indicates that the flash memory array and the buffer cannot be accessed. power on/reset state when power is first applied to the device, or when recover- ing from a reset condition, the device will default to spi mode 3. in addition, the so pin will be in a high impedance state, and a high to low transition on the cs pin will be required to start a valid instruction. the spi mode will be automatically selected on every falling edge of cs by sam- pling the inactive clock state. note: 1. after power is applied and v cc is at the minimum specified data sheet value, the system should wait 20 ms before an oper- ational mode is started. status register format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rdy/busy comp0 01xxx absolute maximum ratings* temperature under bias................................ -55 c to +125 c *notice: stresses beyond those listed under absolute maximum ratings may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -65 c to +150 c all input voltages (including nc pins) with respect to ground ...................................-0.6v to +6.25v all output voltages with respect to ground .............................-0.6v to v cc + 0.6v dc and ac operating range at45db011 operating temperature (case) com. 0 c to 70 c ind. -40 c to 85 c v cc power supply (1) 2.7v to 3.6v
at45db011 7 input test waveforms and measurement levels t r , t f < 5 ns (10% to 90%) output test load dc characteristics symbol parameter condition min typ max units i sb standby current cs , reset , wp = v ih , all inputs at cmos levels 210 m a i cc1 active current, read operation f = 13 mhz; i out = 0 ma; v cc = 3.6v 410ma i cc2 active current, program/erase operation v cc = 3.6v 10 25 ma i li input load current v in = cmos levels 1 m a i lo output leakage current v i/o = cmos levels 1 m a v il input low voltage 0.6 v v ih input high voltage 2.0 v v ol output low voltage i ol = 1.6 ma; v cc = 2.7v 0.4 v v oh output high voltage i oh = -100 m av cc - 0.2v v ac characteristics symbol parameter min typ max units f sck sck frequency 13 mhz t wh sck high time 35 ns t wl sck low time 35 ns t cs minimum cs high time 250 ns t css cs setup time 250 ns t csh cs hold time 250 ns t csb cs high to rdy/busy low 200 ns t su data in setup time 10 ns t h data in hold time 20 ns t ho output hold time 0 ns t dis output disable time 25 ns t v output valid 30 ns t xfr page to buffer transfer/compare time 120 200 m s t ep page erase and programming time 10 20 ms t p page programming time 7 15 ms t pe page erase time 6 10 ms t be block erase time 7 15 ms t rst reset pulse width 10 m s t rec reset recovery time 1 m s ac driving levels ac measurement level 0.45v 2.0 0.8 2.4v device under test 30 pf
at45db011 8 ac waveforms two different timing diagrams are shown below. waveform 1 shows the sck signal being low when cs makes a high- to-low transition, and waveform 2 shows the sck signal being high when cs makes a high-to-low transition. both waveforms show valid timing diagrams. the setup and hold times for the si signal are referenced to the low-to-high transition on the sck signal. waveform 1 shows timing that is also compatible with spi mode 0, and waveform 2 shows timing that is compatible with spi mode 3. waveform 1 C inactive clock polarity low waveform 2 C inactive clock polarity high cs sck si so tcss valid in th tsu twh twl tcsh tcs tv high impedance valid out tho tdis high impedance cs sck si so tcss valid in th tsu twl twh tcsh tcs tv high z valid out tho tdis high impedance
at45db011 9 reset timing (inactive clock polarity low shown) command sequence for read/write operations (except status register read) notes: 1. r designates bits reserved for larger densities. 2. it is recommended that r be a logical 0. 3. for densities larger than 1m bit, the r bits become the most significant page address bit for the appropriate density. cs sck reset so high impedance high impedance si trst trec tcss si cmd 8 bits 8 bits 8 bits msb reserved for larger densities page address (pa8-pa0) byte/buffer address (ba8-ba0/bfa8-bfa0) lsb r r r r r r x x x x x x x x x x x x x x x x x x
at45db011 10 each transition represents 8 bits and 8 clock c y cles write operations the following block diagram and waveforms illustrate the various write sequences available. main memory page program through buffer buffer write buffer to main memory page program (data from buffer programmed into flash page) flash memory array page (264 bytes) buffer (264 bytes) i/o interface si buffer to main memory page program main memory page program through buffer buffer write si cmd n n+1 last byte completes writing into buffer starts self-timed erase/program operation cs r r , pa8-7 pa6-0, bfa8 bfa7-0 si cmd x xx, bfa8 bfa7-0 n n+1 last byte completes writing into buffer cs si cmd pa6-0, x x cs starts self-timed erase/program operation r r , pa8-7 n = 1st byte written n+1 = 2nd byte written
at45db011 11 read operations the following block diagram and waveforms illustrate the various read sequences available. main memory page read main memory page to buffer transfer (data from flash page read into buffer) buffer read flash memory array page (264 bytes) buffer (264 bytes) i/o interface main memory page to buffer main memory page read buffer read so si cmd pa6-0, ba8 ba7-0 x x x x cs n n+1 so r r , pa8-7 si cmd pa6-0, x x starts reading page data into buffer cs so r r , pa8-7 si cmd x xx, bfa8 bfa7-0 cs n n+1 so x each transition represents 8 bits and 8 clock c y cles n = 1st byte read n+1 = 2nd byte read
at45db011 12 detailed bit-level read timing C inactive clock polarity low main memory page read buffer read status register read si 0 10 10 xxx cs so sck 12345 60 61 62 63 64 65 66 67 xx high-impedance d 7 d 6 d 5 data out command opcode msb tsu tv si 0 10 10 xxx cs so sck 12345 36 37 38 39 40 41 42 43 xx high-impedance d 7 d 6 d 5 data out command opcode msb tsu tv si 0 10 10 111 cs so sck 12345 78910 11 12 16 17 high-impedance d 7 d 6 d 5 status register output command opcode msb tsu tv 6 d 1 d 0 d 7 lsb msb
at45db011 13 detailed bit-level read timing C inactive clock polarity high main memory page read buffer read status register read si 0 10 10 xxx cs so sck 12345 61 62 63 64 65 66 67 xx high-impedance d 7 d 6 d 5 data out command opcode msb tsu tv d 4 68 si 0 10 10 xxx cs so sck 12345 37 38 39 40 41 42 43 xx high-impedance d 7 d 6 d 5 data out command opcode msb tsu tv d 4 44 si 0 10 10 111 cs so sck 12345 78910 11 12 17 18 high-impedance d 7 d 6 d 5 status register output command opcode msb tsu tv 6 d 4 d 0 d 7 lsb msb d 6
at45db011 14 table 1 main memory page read buffer read main memory page to buffer transfer main memory page to buffer compare buffer write opcode 52h 54h 53h 60h 84h 00001 11110 00010 11100 00000 01001 10100 00100 rxr rx rxr rx rxr rx rxr rx rxr rx rxr rx pa 8 x pa 8 pa 8 x pa 7 x pa 7 pa 7 x pa 6 x pa 6 pa 6 x pa 5 x pa 5 pa 5 x pa 4 x pa 4 pa 4 x pa 3 x pa 3 pa 3 x pa 2 x pa 2 pa 2 x pa 1 x pa 1 pa 1 x pa 0 x pa 0 pa 0 x b a8 b fa 8 x x b fa 8 b a7 b fa 7 x x b fa 7 b a6 b fa 6 x x b fa 6 b a5 b fa 5 x x b fa 5 b a4 b fa 4 x x b fa 4 b a3 b fa 3 x x b fa 3 b a2 b fa 2 x x b fa 2 b a1 b fa 1 x x b fa 1 b a0 b fa 0 x x b fa 0 xx xx xx xx xx xx xx xx ? ? ? x (64th bit) x (dont care) r (reserved bits)
at45db011 15 x (dont care) r (reserved bits) table 2 buffer to main memory page program with built-in erase buffer to main memory page program without built-in erase page erase block erase main memory page program through buffer auto page rewrite through buffer status register opcode 83h 88h 81h 50h 82h 58h 57h 111 0100 000 1011 000 0000 000 1011 010 0010 000 0001 100 0101 101 0001 rrr rrr rrr rrr rrr rrr rrr rrr rrr rrr rrr rrr pa 8 pa 8 pa 8 pa 8 pa 8 pa 8 pa 7 pa 7 pa 7 pa 7 pa 7 pa 7 pa 6 pa 6 pa 6 pa 6 pa 6 pa 6 pa 5 pa 5 pa 5 pa 5 pa 5 pa 5 pa 4 pa 4 pa 4 pa 4 pa 4 pa 4 pa 3 pa 3 pa 3 pa 3 pa 3 pa 3 pa 2 pa 2 pa 2 x pa 2 pa 2 pa 1 pa 1 pa 1 x pa 1 pa 1 pa 0 pa 0 pa 0 x pa 0 pa 0 x x x x bfa8 x x x x x bfa7 x x x x x bfa6 x x x x x bfa5 x x x x x bfa4 x x x x x bfa3 x x x x x bfa2 x x x x x bfa1 x x x x x bfa0 x
at45db011 16 figure 1. algorithm for programming or reprogramming of the entire array sequentially notes: 1. this type of algorithm is used for applications in which the entire array is programmed sequentially, filling the array page-by- page. 2. a page can be written using either a main memory page program operation or a buffer write operation followed by a buffer to main memory page program operation. 3. the algorithm above shows the programming of a single page. the algorithm will be repeated sequentially for each page within the entire array. start main memory page program (82h) end provide address and data buffer write (84h) buffer to main memory page program (83h)
at45db011 17 figure 2. algorithm for randomly modifying data notes: 1. to preserve data integrity, each page of a dataflash sector must be updated/rewritten at least once within every 10,000 cumulative page erase/program operations within that sector. 2. a page address pointer must be maintained to indi- cate which page is to be rewritten. the auto page rewrite command must use the address specified by the page address pointer. 3. other algorithms can be used to rewrite portions of the flash array. low power applications may choose to wait until 10,000 cumulative page erase/program operations have accumulated before rewriting all pages of the sector. see application note an-4 (using atmels serial dataflash) for more details. start main memory page to buffer transfer (53h) increment page address pointer (2) auto page rewrite (2) (58h) end provide address of page to modify if planning to modify multiple bytes currently stored within a page of the flash array main memory page program (82h) buffer write (84h) buffer to main memory page program (83h) sector addressing pa 8 pa 7 pa 6 pa 5 pa 4 pa 3 pa 2 - pa0 sector 000000 x 0 0xxxxx x 1 1xxxxx x 2
at45db011 18 ordering information f sck (mhz) i cc (ma) ordering code package operation range active standby 13 10 0.01 AT45DB011-JC at45db011-sc at45db011-xc 32j 8s2 14x commercial (0 c to 70 c) 13 10 0.01 at45db011-ji at45db011-si at45db011-xi 32j 8s2 14x industrial (-40 c to 85 c) package type 32j 32-lead, plastic j-leaded chip carrier (plcc) 8s2 8-lead, 0.210" wide, plastic gull wing small outline (eiaj soic) 14x 14-lead, 0.170" wide, plastic thin shrink small outline package (tssop)
at45db011 19 packaging information 32j , 32-lead, plastic j-leaded chip carrier (plcc) dimensions in inches and (millimeters) jedec standard ms-016 ae .045(1.14) x 45 pin no. 1 identify .025(.635) x 30 - 45 .012(.305) .008(.203) .021(.533) .013(.330) .530(13.5) .490(12.4) .030(.762) .015(3.81) .095(2.41) .060(1.52) .140(3.56) .120(3.05) .032(.813) .026(.660) .050(1.27) typ .553(14.0) .547(13.9) .595(15.1) .585(14.9) .300(7.62) ref .430(10.9) .390(9.90) at contact points .022(.559) x 45 max (3x) .453(11.5) .447(11.4) .495(12.6) .485(12.3) 8s2 , 8-lead, 0.210" wide, plastic gull wing small outline (eiaj soic) dimensions in inches and (millimeters) .020 (.508) .012 (.305) .213 (5.41) .205 (5.21) .330 (8.38) .300 (7.62) pin 1 .050 (1.27) bsc .212 (5.38) .203 (5.16) .080 (2.03) .070 (1.78) .013 (.330) .004 (.102) 0 8 ref .010 (.254) .007 (.178) .035 (.889) .020 (.508) 14x , 14-lead, 0.170" wide, thin shrink small outline package (tssop) dimensions in millimeters and (inches)* *controlling dimension: millimeters 5.10 (.201) 4.90 (.193) 1.20 (.047) max .650 (.026) bsc 0.20 (.008) 0.09 (.004) 0.15 (.006) 0.05 (.002) index mark 6.50 (.256) 6.25 (.246) seating plane 4.50 (.177) 4.30 (.169) pin 1 0.75 (.030) 0.45 (.018) 0 8 ref 0.30 (.012) 0.19 (.007)

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